The present invention relates to a semiconductor device and its manufacturing technique, in particular, to technology which is effective when applied to a miniaturized semiconductor device and its manufacturing.
Published Japanese translation of PCT patent application No. 2008-506262 (Patent Document 1) describes a semiconductor device comprising a multilayer nitride stack having nitride etch stop layers formed by lamination, wherein each of the nitride etch stop layers is formed using a film formation process. A method of forming a multilayer nitride stack includes the steps of arranging a substrate in a single wafer deposition chamber and applying a thermal shock to the substrate immediately before deposition. A first nitride etch stop layer is deposited over the substrate. A second nitride etch stop layer is deposited over the first nitride etch stop layer. At this time, it is assumed that the first nitride etch stop layer and the second nitride etch stop layer have the same film thickness.
International Patent Publication No. WO2002/043151 Pamphlet (Patent Document 2) describes the method of generating tensile stress in an n-channel MISFET to generate compression stress in a p-channel MISFET using a self-alignment silicon nitride film. It further describes the method of forming a silicon nitride film that causes the n-channel MISFET to generate tensile stress and laminating a silicon nitride film that causes the p-channel MISFET to generate tensile stress and a silicon nitride film that causes the p-channel MISFET to generate compression stress. Then, an example etc. is disclosed, which while causing the n-channel MISFET to generate tensile stress, relaxes tensile stress generated in the p-channel MISFET.